SanFranRecruiter Since 2001
the smart solution for San Francisco jobs

Design Verification Engineer System Verilog UVM

Company: CyberCoders
Location: San Francisco
Posted on: August 7, 2022

Job Description:

If you are a Design Verification Engineer System Verilog UVM with experience, please read on!

Top Reasons to Work with Us

I have multiple opportunities available for this role including in Austin Texas, San Francisco California, and Redmond Washington.

What You Need for this Position

BS or MS in Computer Science or Electrical Engineering.

" 5-10+ years of industry experience bringing silicon ICs into high volume production.

" Must have strong experience with UVM.

" Must have a full chip verification experience

" Experience of leading a single project.

" Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Real Time.

" Sound knowledge of ARMv8, interconnect, memory coherence and memory architectures

" Familiarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verification)

" Expertise in writing Perl / Python , awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers.

" Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation

" Experience with low-level programming of systems in C/C++.

" Experienced in writing scripts in languages such as Perl, Python, and Tcl.

" Functional understanding of constrained random verification process, functional coverage, and code coverage.

" Low power verification UPF

" Team player with excellent communication skills and the desire to take on diverse challenges.

" Customer interaction

What's In It for You

Salary $140k-$250k

So, if you are a Design Verification Engineer System Verilog UVM with experience, please apply today!

Email Your Resume In Word To

Looking forward to receiving your resume through our website and going over the position with you. Clicking apply is the best way to apply, but you may also:

Austin.Massey@CyberCoders.com

  • Please do NOT change the email subject line in any way. You must keep the JobID: linkedin : AM24-1697196L498 -- in the email subject line for your application to be considered.***
    Austin Massey - Recruiter - CyberCoders

    Applicants must be authorized to work in the U.S.

    CyberCoders, Inc is proud to be an Equal Opportunity Employer

    All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.

    Your Right to Work - In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification document form upon hire.

Keywords: CyberCoders, San Francisco , Design Verification Engineer System Verilog UVM, Other , San Francisco, California

Click here to apply!

Didn't find what you're looking for? Search again!

I'm looking for
in category
within


Log In or Create An Account

Get the latest California jobs by following @recnetCA on Twitter!

San Francisco RSS job feeds