Design For Test/Automation Engineer
Location: San Mateo
Posted on: September 15, 2018
At SiFive, youll be part of a fun, engaging team and be afforded the opportunity to grow within the company. You will work side-by-side with the founders of RISC-V and bring to fruition the new RISC-V architecture and enable its rapid adoption by implementing new tools, breakthrough design methods and services. We need people who are trail-blazers, arent afraid to take a chance, and dont always go with the flow. This Engineer will help automate the methodology inside a small team focused on Implementation of RISC-V SOCs, from synthesis to GDS. A strong learner and an effective communicator, they will help automate different aspects of the design flow, starting with the Design For Test.Responsibilities
- All things DFT: scan, boundary scan/JTAG, at-speed scan, scan compression, memBIST.
- Flat and hierarchical DFT insertion and verification.
- Chip-level and block-level DFT insertion and verification.
- Generate test patterns and achieve coverage targets.
- Integrate complex 3rd party IPs -- such as DDR, PCIe, USB, etc. -- into overall DFT framework.
- Automation of DFT features into overall implementation framework.
- Work with ATE or test engineers for cost reduction, yield analysis and optimization.
- Comprehensive DFT insertion experience: scan, boundary scan/JTAG, at-speed scan, scan compression, memBIST.
- DFT insertion experience using either flat or hierarchical flow.
- DFT insertion experience at both block level and chip level.
- Experience in semiconductor test, characterization, and manufacturing test.
- Experience integrating complex 3rd party IPs with pre-inserted DFT -- such as DDR, PCIe, USB, etc. -- into overall DFT framework.
- Experience with formal logic equivalence checking (LEC)
- Experience with Synopsys Design Constraints (SDC) and multi-mode multi-scenario analysis (MMMC) pertaining to DFT.
- Scripting and automation experience: Perl, shell, python, ruby, makefile, Tcl programming experience.
Nice to Have
- Experience managing semiconductor test yield
- Experience with version control systems such as GIT, Perforce, Subversion, etc.
- RTL coding experience and architectural knowledge.
- Knowledge of commercial processor cores.
- Exposure to physical implementation and how DFT affects it.
- Experience in memory BIST & repair (BISR, BIRA)
We are looking for someone with broad experience who is comfortable working independently and open to innovation in the design process to grow our small team and work with a wide variety of circuits, systems and applications.SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off, health, vision and dental benefits, 401(k) plan, employee stock option program, and much more. If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is the place for you!
Keywords: SiFive, San Francisco , Design For Test/Automation Engineer, Engineering , San Mateo, California
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