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Verification Engineer - C/C++

Company: Experis Engineering
Location: San Francisco
Posted on: May 17, 2018

Job Description:

Experis is currently engaged with several chip manufacturers and seeking Verification Engineers in the Silicon Valley Area. Long term opportunity in Silicon Valley! This role will own ATE/MFG tests (work on SoC tests). The successful candidate needs to be good at C/C++/Verilog/SV. UVM is a nice to have. Would prefer to have NAND/DDR knowledge. NVMe nice to have. Lab debugging experience of silicon would be useful. Cultural match includes: Ability to work under pressure, ability to keep a cool head, working with team and delivering results. Prefer 3-5 years.

Keywords: Experis Engineering, San Francisco, Verification Engineer - C/C++, Engineering, San Francisco, California

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